Radar systems and radar devices typically utilize millimeter wave (MMW) frequencies for transmission and reception. The frequency generation circuits (sometimes referred to as synthesizers) of such radar devices typically comprise a phase detector and a voltage controlled oscillator (VCO), as part of a phase locked loop (PLL), which is responsible for the generation of the millimeter wave frequencies. Generally, voltage controlled oscillators operating at millimeter wave frequencies need to present a low phase noise, whilst providing a wide tuning range in order to cover the required modulation band (e.g. 1 GHz for Long-Range Radar (LRR) and 4 GHz for Short-Range Radar (SRR)). As such, VCO designs in radar applications are complex and suitable designs to meet all performance requirements are far from trivial.
Voltage controlled oscillators operating at millimeter wave frequencies generally suffer from center frequency variation over extreme corners and temperature conditions. Such center frequency variations tend to reduce the available tuning range of these VCOs, which can limit the modulation bandwidth, thereby resulting in increased manufacturing yield losses.
In a typical PLL, the VCO exhibits a frequency variation across the frequency-tuning voltage (Vtune) applied to the VCO. The gain of the VCO is the derivative of the frequency vs. Vtune. Changes to the VCO gain impacts the gain of the loop, and thus, in effect, the loop bandwidth varies with the VCO gain. Other loop parameters, such as stability margin, rejection of the spurious tone created by the reference frequency of the PLL, response time, phase noise, etc., are also affected by any variation of the VCO parameters with Vtune. As a consequence, PLL designs typically need to optimize the loop stability for the worst-case VCO performance, which leads to a degraded phase noise and a poorer PLL response time.
U.S. Pat. No. 7,508,277 B2 describes a phase locked loop with VCO tuning sensitivity compensation. In U.S. Pat. No. 7,508,277 B2, phase detector gain is tuned step-wise by adapting the phase detector bias current through a feedback loop function of Vtune. Thus, the Vtune voltage that forms the input of the feedback loop needs to be measured, and this is likely to degrade the phase noise of the VCO in most practical scenarios. Furthermore, it is known that such methods of adjusting the gain of the phase detector to control the loop bandwidth of a PLL result in a relatively complicated design.
US 20080111642 A1 describes an apparatus and method for VCO linearization where the VCO gain is linearized at the expense of the VCO tuning range. This proposed design requires use of low-noise bias voltages, which makes the design complex.